1. Field of the Invention
The invention relates to methods of fabrication of integrated circuits, more particularly to etching steps required to form metallic interconnections.
2. Discussion of the Related Art
In present integrated circuit fabrication techniques, vertical connections need to be made to semiconductor devices within the integrated circuit. These are usually made by covering the semiconductor devices with an interlevel dielectric layer, such as a silicon dioxide (SiO.sub.2) layer, and etching narrow, vertical holes through this dielectric layer to expose portions of the underlying device. These holes are filled with a conductive material such as tungsten, aluminum or titanium to form contacts, and an interconnect layer is applied over the surface so produced. The interconnect layer is in electrical contact with the semiconductor device, and may be patterned by etching, to define interconnect wiring.
Several conductive layers, composed of metallic materials such as tungsten, copper, aluminum, titanium, or alloys of such metals, are often used. To join together these layers, vertical connections (vias) are used.
FIG. 1 shows a cross section of a partly finished integrated circuit. A semiconductor substrate 10 of a first conductivity type contains source 15 and drain 20 regions saving a second conductivity type, opposite to the first. Lightly doped drain (LDD) structures 25 may be provided adjacent to the source 15 and drain 20 regions. A transistor gate insulator 30 lies on the semiconductor surface, between the source 15 and drain 20. A gate electrode 35 lies over the gate insulator 30. These features form a standard MOS transistor 37. A first interlevel dielectric layer 40 has been deposited over the structure. Contact holes 45, 50, 55 have been etched through the dielectric layer 40 above drain 20 gate 35 and source 15 regions, respectively. The contact holes are filled with a conductive material 60 according to any suitable process. A first interconnect layer 64 has been deposited, and patterned with an etch step to form interconnect wiring 67, 70, 75 in electrical contact with drain 20, gate 35, and source 15 regions, respectively.
The contact holes 45, 50, 55 and wiring 67, 70, 75 are usually formed by plasma etching, such as reactive ion etching (RIE). During such etch steps, significant electrical charges build up on metallic parts of the structure. When a long wiring has been formed, its entire length acts to collect charge. In a complex integrated circuit, a single wiring may attain a length of several meters.
Any charge that builds up on wirings 67, 75 may be dissipated through the diode junction formed by the substrate 10 and the drain 20 or source 15 regions, respectively. According to the polarity of the charge and the conductivity types of the source, drain and substrate, this dissipation may either be by forward bias conduction of the diode junction, or reverse bias leakage current of the same diode. The conduction is represented in the figure by arrows 77.
For charge built up on wiring 70, no such discharge path is available. The wiring is insulated from the substrate 10 by gate insulator 30. A charge builds up, illustrated in the figure by "+" signs around the gate 35, contact 60 and wiring 70, although the charge could be of either polarity. This charge causes a high voltage to be present across the gate insulator 30, causing stress and weakening that gate insulator. Such weakening will reduce the lifetime and the overvoltage immunity of the finished integrated circuit.
It has been proposed to connect a diode in parallel with the gate insulator 30, to provide a leakage path to the substrate for the charge. This however causes a leakage current during the operation of the integrated circuit.
In view of the foregoing, it is an object of the present invention to provide a method of fabricating contacts in integrated circuits which does not allow charge build up on wiring of the circuit.
It is a further object of the present invention to provide such a method which does not cause parasitic leakage current to flow from the gate during operation of a finished integrated circuit.
It is a further object of the present invention to provide such a method which does not significantly lengthen the fabrication time of integrated circuits.